In this episode of Bugged Out, Harry Foster talks with Chandu Challapalli, Senior Management Director at Siemens EDA, about why timing constraints must be treated as first-class verification assets. Drawing on insights from his white paper, A Guide to SDC-Based Timing-Intent Verification with Questa One, Chandu explains how automated SDC verification uncovers hidden timing risks, balances under- and over-constraining, and shifts timing validation earlier in the design cycle. Learn how Questa One brings structure and automation to timing-intent verification—helping teams achieve faster signoff and greater confidence in first-pass silicon success. Key Discussion Points Why Timing Constraints Matter: How SDC files capture design intent—and why ignoring their verification invites silicon risk. What Is Timing-Intent Verification?: A clear explanation of validating clocks, exceptions, and constraints against real design behavior. Finding the Right Balance: The hidden costs of under-constraining versus over-constraining timing. Common SDC Pitfalls: Missing clocks, invalid exceptions, and legacy constraints that mask real bugs. Shifting Left on Timing: Why verifying constraints early—alongside RTL—reduces late-stage surprises. What’s Next: A glimpse into continuous, AI-assisted timing-intent verification and tighter frontend/backend alignment.
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14 mins